I guess that's logical, a higher voltage cap with the same capacitance will be much larger to support the higher breakdown voltage. I don't know if DF is the big problem in that circuit node but generally why use one there at all?Craig Buckingham wrote:Hi Guys, new here, first post.mediatechnology wrote:Thanks John.
After looking at it I realized that the input has a 1.6 Hz cutoff, the C5/R13 cutoff 0.6 Hz.
With the input rolled off early I doubt C5 wouldn't see any significant terminal voltage.
Probably best to just series-connect two 220 uF.
Wonder why he specified a 100V rating?
Easily done with 2X 220uF/50V but a lot of real estate.
My guess it was chosen for low dissipation factor. Generally higher voltage electrolytics have lower dissipation factors for the same capacitance value.
I don't think I've mentioned it in this thread yet.. but back in the '70s my first preamp design was an almost app note stock LM387 nat semi. My primary deviation from stock, was a minor circuit tweak to suffer less deviation from 75uSec above 20kHz but still had the unity gain asymptote. I did a later review of the large electrolytic to ground to generate the high LF gain. In my case it was a 22uF aluminum electrolytic and 360 Ohm R. In bench tests I measures a few tens of degrees less phase shift at 20 kHz from a 22uF tantalum cap vs. the cheap aluminum. I sent replacement caps to about a dozen kit owners and asked them to swap them out tell me what they though. The few who did that reported an improvement, but this is not a scientific test, and electrolytic caps have improved dramatically since the 70s.
agreed... DCAlso, calmart, you mentioned in a later post about avoiding C3 and C5 electrolytics. I like to avoid electrolytics also. Although C3 is in a benign DC location and not going to cause any noticeable harm.
worst case +/- 0.7mV typical +/- 0.1mV (yes late)C5 however is likely to harm things. It's late here and I am a bit sleepy, so I'll try and get this right. The LM4562 has worst case I/P offset voltage of +/-700mV and I/P offset current of 65nA. Looking at the inverting terminal only,
I calculate 2.4mV DC error from Ib alone, +/- 43 mV from worst case input offset voltage, while there is no expectation that the first stage will output anywhere close to 0V DC.I make it a DC Av of (61.67) with R13 connected to ground. The 65nA of I/P offset current works out to be 186.5uV offset voltage across R13. Added to a worst case of 7mV I/P offset voltage = 886.5uV I/P offset voltage. Multiplied by the DC Av 61.67 gives +/-54.67mV output offset voltage. Mind you these are worst case and the typicals are a factor of 7 better than this. Which would be around +/- 7.8mV O/P offset for the last stage.
The TI app note shows an all DC coupled RIAA stage that probably doesn't suck, these modern op amps are pretty good.
Yup a DC trim or maybe a servo... Speaking of the published design why cap couple the JFET input? I have DC coupled all the JFET input phono preamps I made with no issue (AFAIK). If you want to add a HPF pole like maybe IEC's proposed 30Hz pole, I'de use a film cap between gain stages. But phono preamps are like so last century...How much DC can the next stage take is the big question. The offset could be trimmed out without too much effort with a bias current compensation scheme.
JR