DC Feedback Stabilizes Bias On FET/Bipolar Pair, 1970

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mediatechnology
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DC Feedback Stabilizes Bias On FET/Bipolar Pair, 1970

Post by mediatechnology »

DC Feedback Stabilizes Bias On FET/Bipolar Pair," Howard Russell, Texas Instruments, EDN, November 15, 1970.

This is another article that I've been saving for 40+ years that has limited availability on the web.

Image
"DC Feedback Stabilizes Bias On FET/Bipolar Pair," Howard Russell, Texas Instruments, EDN, November 15, 1970.

DC Feedback Stabilizes Bias On FET/Bipolar Pair," Howard Russell, Texas Instruments, EDN, November 15, 1970.
Full pdf: https://proaudiodesignforum.com/images/ ... 5_1970.pdf
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JR.
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Re: DC Feedback Stabilizes Bias On FET/Bipolar Pair, 1970

Post by JR. »

OK but what is the circuit doing besides managing the JFET bias?

#1 the input voltage swing will be modest as too much negative swing will saturate the current source.
#2 with the source of the JFET loaded by a current source the circuit has no voltage gain.

Is this part of some larger circuit ?

JR
Last edited by JR. on Mon Oct 20, 2014 12:49 pm, edited 1 time in total.
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mediatechnology
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Re: DC Feedback Stabilizes Bias On FET/Bipolar Pair, 1970

Post by mediatechnology »

Is this part of some larger circuit ?
Not that I'm aware of.
Isn't Q1 simply serving as a high-impedance buffer for Q3?
I liked the circuit because it was really old. :lol:
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JR.
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Re: DC Feedback Stabilizes Bias On FET/Bipolar Pair, 1970

Post by JR. »

mediatechnology wrote:
Is this part of some larger circuit ?
Not that I'm aware of.
Isn't Q1 simply serving as a high-impedance buffer for Q3?
I liked the circuit because it was really old. :lol:
There is probably one or more components missing.

The collector of Q2 is a high impedance so signal in the JFET will not cause a current change at base of Q3, so no output voltage.

JR
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Craig Buckingham
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Re: DC Feedback Stabilizes Bias On FET/Bipolar Pair, 1970

Post by Craig Buckingham »

That's right JR.

An electrolytic capacitor in series with a gain setting resistor from the source of the FET to ground will make it work for AC signals.

EDIT: I stand corrected. The second stage has an AC gain of around 288. First stage gain could be in the range of 0.068 for a current sink impedance of 1MΩ. That gives an overall AC gain of around 19.

EDIT2: Gawd, I am rusty. First stage gain is lower. Forgot base impedance of Q3. For a Hfe of 200 the first stage gain is going to be a lot lower, maybe around .0048. Maybe AC gain around 1.39. Hfe of Q3 and impedance of current sink Q2 are going to affect the gain of this substantially.

So the first point I made would put more gain into the first stage.
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