Incorporating HPF in the FET input stage

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ilya
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Incorporating HPF in the FET input stage

Post by ilya » Mon Dec 11, 2017 1:00 pm

I'm building a simple FET DI input and it has too wide bandwidth as it is. What is the best way to incorporate an LPF in this design? I've tried different things, but the most obvious is a cap across the resistor as shown (470p gives a good cut-off frequency).

Are there any drawbacks to this method? Maybe there're some other solutions?

Thanks!
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JR.
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Re: Incorporating HPF in the FET input stage

Post by JR. » Mon Dec 11, 2017 2:48 pm

Your added cap is simply a shunt across the input so LPF results will vary with the source impedance of the instrument plugged in.

To make it better behaved you can add a fixed resistance in series with C50, but there is no free lunch that added R will contribute noise of it's own. That added series R wants to be high impedance wrt source, but not so high that it adds audible noise...

You can probably experiment with a few different Rs to see what works for you.
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Another option is to use the series output R (100 ohm) as the R in your RC LPF but that will require a larger value C. That r could be increased to 200 ohms or more with little consequence.

JR

ilya
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Re: Incorporating HPF in the FET input stage

Post by ilya » Mon Dec 11, 2017 3:28 pm

Series Rin will be too noisy. I estimated a suitable R as 500K, which gave me a -97dBv Johnson noise.

Cap on the output worked though. Where is it better to connect it? Before R56 or after? I'm getting different values of the cap depending on its position (roughly 100 times difference in capacitance).

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JR.
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Re: Incorporating HPF in the FET input stage

Post by JR. » Mon Dec 11, 2017 5:30 pm

It must be after R56 to work... that is the R of the RC.

JR

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mediatechnology
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Re: Incorporating HPF in the FET input stage

Post by mediatechnology » Tue Dec 12, 2017 6:26 am

Just my 2 cents but wouldn't you want some small (1K-ish or less) series resistance with the input to reduce RF rectification and protect the gate?
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JR.
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Re: Incorporating HPF in the FET input stage

Post by JR. » Tue Dec 12, 2017 10:25 am

mediatechnology wrote:
Tue Dec 12, 2017 6:26 am
Just my 2 cents but wouldn't you want some small (1K-ish or less) series resistance with the input to reduce RF rectification and protect the gate?
Probably good practice but won't make a well defined R for a LPF since source impedance will add to that 1k.

JR

Note: placing the RC at the output buildout R will also interact with load capacitance (like cable capacitance) but that should be small wrt expected C value.

ilya
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Re: Incorporating HPF in the FET input stage

Post by ilya » Tue Dec 12, 2017 1:33 pm

Tried several things and cap on the output worked the best. No traces of high frequency garbage that was otherwise getting inside the circuit (even with the cap on the input). Thanks gents! I'll insert the 1K protecting resistor at the input as well.

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mediatechnology
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Re: Incorporating HPF in the FET input stage

Post by mediatechnology » Tue Dec 12, 2017 2:18 pm

Probably good practice but won't make a well defined R for a LPF since source impedance will add to that 1k.
That suggestion wasn't intended to make it a LPF - just some R in series with the gate for HF and VHF RFI.
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JR.
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Re: Incorporating HPF in the FET input stage

Post by JR. » Tue Dec 12, 2017 4:19 pm

mediatechnology wrote:
Tue Dec 12, 2017 2:18 pm
Probably good practice but won't make a well defined R for a LPF since source impedance will add to that 1k.
That suggestion wasn't intended to make it a LPF - just some R in series with the gate for HF and VHF RFI.
You mentioned preventing rectification... There will be a LPF from stray capacitance (and 1k) but a modest C to ground would be more reliable.

For a one off, do what works...

JR

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